An electrostatic discharge (ESD) pulse is a sudden and unexpected voltage and/or current discharge that transfers energy to an electronic device from an outside body (e.g., a human body, which can be approximated in modeling by a human body model (HBM)). ESD pulses can damage electronic devices, for example by “blowing out” a gate oxide of a transistor in cases of high voltage or by “melting” an active region area of a device in cases of high current, causing junction failure. If devices are damaged by an ESD pulse, the electronic product can be rendered less operable than desired, or can even be rendered inoperable altogether.
To protect electronic devices from ESD pulses, engineers have developed ESD protection devices. FIG. 1 shows an example of an integrated circuit 100 that includes an ESD-susceptible circuit 102 (e.g., one or more semiconductor devices) electrically connected to an exterior circuit assembly (not shown) via an external IC pin 104. The external IC pin 104 can be a supply pin that supplies a DC supply voltage (e.g., VDD or VSS) to the circuit 102, or can be an input/output (I/O) pin that transfers input or output signals there from, for example. A conventional ESD protection device 106 is electrically connected between the circuit 102 and the external pin 104 to mitigate damage due to an ESD pulse 108. If an ESD pulse 108 occurs, the ESD protection device 106 detects the ESD pulse 108 and shunts the energy associated with it away from the circuit 102 (e.g., as shown by arrow WESD), thereby preventing damage to the circuit 102. In the absence of an ESD pulse 108, the ESD protection device 106 is off and thus leaves signals between circuit 102 and pin 104 unchanged.
Although ESD devices are well known and widely deployed, the inventors have appreciated that conventional ESD protection devices suffer from some shortcomings. One particular shortcoming arises when designers want to move to a new technology node that includes lower voltage devices, relative to previous technology nodes. In some instances, the designers may want to use the newer, lower-voltage devices for a first on-chip circuit (e.g., >having 2.5V devices), while using higher-voltage devices for a second on-chip circuit (e.g., having 5 V devices). If an ESD protection device made up of lower-voltage devices (e.g., >2.5 V devices) were to be used as an interface to the second, higher-voltage circuit, the low-voltage devices would potentially be unable to reliably withstand the high-voltage signal (e.g., 5V). One way to alleviate this problem is by using two different gate oxide thicknesses—namely, a first, relatively thin gate oxide for the ESD protection device interfacing to the first, low voltage circuit; and a second, relatively thick gate oxide for the ESD protection device interfacing to the second, higher voltage circuit. Unfortunately, however, two different gate oxide thicknesses on a single IC requires a significant number of masks, and is therefore not an optimum solution. Also, a thicker gate oxide for an ESD protection device tends to lead to high trigger voltages and/or the ESD protection device being slow to turn on when an ESD event is detected. Either of these conditions can potentially allow some of the power in the ESD pulse to reach the ESD susceptible circuit, potentially damaging the ESD susceptible circuit.
In view of the above, the inventors have devised improved ESD protection techniques.